“Quick analysis of the A6 SoC photos from the iPhone 5 launch event tells us all we need to know about the memory interface, speed and bandwidth of the new platform,” Anand Lal Shimpi and Brian Klug report for AnandTech.
“Apple thankfully didn’t obscure the details of its A6 slide at the launch event, which gave us a Samsung part number: K3PE7E700F-XGC2,” Lal Shimpi and Klug report. “The K3P tells us we’re looking at a dual-channel LPDDR2 package with 32-bit channels. The E7E7 gives us the density of each of the two DRAM die (512MB per die, 1GB total). The final two characters in the part number give us the cycle time/data rate, which in this case is 1066MHz.”
Read more in the full article here.
In a related reports, Anand Lal Shimpi explains further, “Given Apple’s reliance on fully licensed ARM cores in the past, the expected performance gains and unpublishable information that started all of this I concluded Apple’s A6 SoC likely featured two ARM Cortex A15 cores.”
“It turns out I was wrong. But pleasantly surprised,” Lal Shimpi reports. “The A6 is the first Apple SoC to use its own ARMv7 based processor design. The CPU core(s) aren’t based on a vanilla A9 or A15 design from ARM IP, but instead are something of Apple’s own creation… I should probably give Apple’s CPU team more credit in the future.”
Lal Shimpi reports, “This is a huge deal for Apple. It puts the company in another league when it comes to vertical integration. The risks are higher (ARM’s own designs are tested and proven across tons of different devices/platforms) but the payoff is potentially much greater.”
Much more in the full article here.