“The most challenging part of last year’s iPhone 5s review was piecing together details about Apple’s A7 without any internal Apple assistance,” Anand Lal Shimpi reports for AnandTech. “I had less than a week to turn the review around and limited access to tools (much less time to develop them on my own) to figure out what Apple had done to double CPU performance without scaling frequency.”
“The end result was an (incorrect) assumption that Apple had simply evolved its first ARMv7 architecture (codename: Swift),” Lal Shimpi reports. “Based on the limited information I had at the time I assumed Apple simply addressed some low hanging fruit (e.g. memory access latency) in building Cyclone, its first 64-bit ARMv8 core.”
Lal Shimpi reports, “By the time the iPad Air review rolled around, I had more knowledge of what was underneath the hood: ‘As far as I can tell, peak issue width of Cyclone is 6 instructions. That’s at least 2x the width of Swift and Krait, and at best more than 3x the width depending on instruction mix. Limitations on co-issuing FP and integer math have also been lifted as you can run up to four integer adds and two FP adds in parallel. You can also perform up to two loads or stores per clock.’ …Although I empirically verified many of Cyclone’s features in advance of the iPad Air review last year, today we have some more concrete information on what Apple’s first 64-bit ARMv8 architecture looks like.”
Much more in the full article – recommended – here.
[Thanks to MacDailyNews Reader “Dan K.” for the heads up.]