“With energy efficiency creeping up enterprises’ evaluation criteria list, Intel knew it couldn’t afford to allow its future chips to use more power. The Santa Clara, Calif., company went back to the drawing board to create a new chip architecture—a replacement for the circuitry that underpins its entire x86 product line—that would both increase performance and cut power consumption,” John G. Spooner writes for eWeek. “Intel will roll out three dual-core chips based on the new Intel Core Microarchitecture later this year… One major change along these lines was the addition of the ability to execute four instructions in a single clock cycle.”
“Intel also chose to use a 14-stage pipeline, and designers cut onboard cache access times and beefed up the ways in which data is prefetched from system memory to ensure that processor cores aren’t kept waiting… The 14-stage pipeline is slightly longer than the ‘Banias’ architecture behind the company’s Core Duo notebook chip, which has 12 stages. But it’s still about half the length of later Pentium 4 processors, which process only between one and three instructions per clock cycle,” Spooner reports. “The new architecture will allow chips such as Intel’s dual-core ‘Woodcrest’ server processor, due in the third quarter, to offer a 35 percent reduction in power consumption with an 80 percent bump in performance over the current Xeon DP processor.”
Full article here.
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