Intel reveals first glimpse of quad-core ‘Clovertown’ chip coming later this year

“Just as the bragging rights for dual-core chip supremacy are dying down, Intel gave the first glimpse of a quad-core chip coming next year,” Michael Kanellos reports for CNET News. “Clovertown, a four-core processor, will start shipping to computer manufacturers late this year and hit the market in early 2007. Clovertown will be made for dual-processor servers, which means that these servers will essentially be eight-processor servers (two processors x four cores each).”

“Core expansion will be a dominant theme for Intel over the next few years, said Chief Technology Officer Justin Rattner. By the end of the decade, chips with tens of cores will be possible, while in 10 years, it’s theoretically possible that chips with hundreds of cores will come out, he added,” Kanellos reports. “Rattner showed off a computer running two Clovertown processors… Clovertown and Tigerton are members of a new chip architecture coming from Intel at the end of the year. A notebook chip called Merom and a desktop chip called Conroe coming out around the same time will be based on the same architecture. Intel will give the architecture a name at the Intel Developer Forum taking place in March. Rattner indicated that Merom and Conroe will only be dual-core chips, as many analysts expect.”

“At around the same time, after all, Intel will release Woodcrest, a dual core server chip based around the same Merom-Conroe-Tigerton-Clovertown architecture. It will contain only two cores and consume 80 watts of power, less than the 165-watt server chips Intel sells now,” Kanellos reports. “A large financial institution is currently running servers on an experimental basis with Woodcrest chips, Rattner said.”

Full article here.

[Thanks to MacDailyNews reader “Andy C.” for the heads up.]

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New IBM Power chip breaks speed barriers, promises to be twice as fast as Sun, Intel, AMD chips – February 08, 2006


  1. Who cooks up these processor names at Intel?

    To Tom Ferguson: You’re mistaken. Mac users have ALWAYS been the coolest people around. If you consider Alienware DOS-Boxes cool… well…

    It certainly WILL be interesting to see what Apple cooks up to house these new processors.

  2. To the tune of “Funkytown”:

    “…Won’t you take me to….Clovertown….

    ….Won’t you take me to….Clovertown….

    ….Aaaaaahhh, talk about it, talk about it, talk about moo-ooo-vin…”

    MDN magic word, “Dumb”

    As in “Dumb and Dumber”

  3. I recently watched the Megahertz Myth video demonstration (yes, again), and I have a question.

    For those who haven’t seen it, you can see it here:

    Now, I am not a chip architecture designer, but I am curious about one thing in this video.

    First, Jobs states that for the test the G4 outperformed the Pentium by 80% for the same task. I have no reason to doubt this.

    In the demo, John highly emphasizes the length of the pipeline. I come away from watching it thinking shorter pipeline = better performance. What the video doesn’t show is that for every ONE processor cycle or ‘tick’ the G4 takes, the Pentium should take TWO (given that the Pentium has twice the clock speed). The demo basically shows both chips running at the same clock speed – tick for tick. Should it not be ‘tick’ (G4) for ‘tick-tick’ (Pentium)? I am curious as to what others think about this or if anyone can clarify it.

    Since higher clock speeds = more heat dissipation. I assume that is why the trend in the industry is now to go with multi-core chips with slightly lower clock speeds. But, doesn’t a program ITSELF have to specifically take advantage of a dual core design, or does the chip take care of this on it’s own? The reason I ask is because there have been issues with Pentium D processors which are also dual-core.

    I would be grateful for any insight into this. Thanks.

  4. Not a chip designer either, but a simple tick/tick graph like John showed can’t explain the whole, complex process.

    In addtion to tick speeds down a pipeline there’s also, I believe, a difference as the G4 ran using RISC (Reduced Instruction Set Code) versus CISC (Complex Instruction Set Code) in the Windows world. RISC runs faster as it doesn’t have to call other code as often as CISC does. It’s something like a staightforward code running down 7 pipelines is faster than a complex code running down 20 pipelines at a faster speed. And you’re looking at a video explaining the difference of chips, two generations past. We’re now in the world of multiple processing cores on a single chip which introduces a whole new way of assessing performance.

    As far as “doesn’t a program ITSELF have to specifically take advantage of a dual core design,” I believe OSX (this isn’t Windows after all) takes care of this, unlike the situation where a program specifically has to be written to take advantage of a 64 bit processor. Hence, The Other Steve’s comment above that Apple has “already designed a computer designed to handle “hundreds of cores,” it’s called the G5 tower.” OS X juggles the cores, not the program.

    If I’ve said anything misleading, I’m sure I’ll be corrected.

  5. As far as “doesn’t a program ITSELF have to specifically take advantage of a dual core design,” I believe OSX (this isn’t Windows after all) takes care of this,

    OSX is no different than Windows in this manner–both have a built in scheduler that assigns threads across multiple processors (whether dual core or dual processor). A program just has to be multithreaded (not physically determine if a dual processors is there), the scheduler (whether OSX or Windows) takes care of the rest.

  6. I remember seeing an inmage from someones developer machine that was a screen capture showing eight processors in the About This Mac” screen. Perhaps someone at Apple has already been privy to some early exapmles of this chip?

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