“Taiwan Semiconductor Manufacturing Company (TSMC) has started commercial production of chips built using 7nm process technology, according to company CEO CC Wei,” Monica Chen and Jessie Shen report for DigiTimes. “The foundry is also scheduled to move a newer 5nm node technology to mass production at the end of 2019 or early-2020, said Wei.”
“Orders for Apple’s custom A12 processor for use in the upcoming iPhones will play a major driver of TSMC’s 7nm chip production growth in 2018, according to market sources,” Chen and Shen report. “The foundry has secured 7nm chip orders from about 20 customers including AMD, Bitmain, Nvidia and Qualcomm. The majority of the orders will be carried out in the first half of 2019, the sources said.”
“As for TSMC’s 5nm node, risk production is scheduled to kick off in the first half of 2019, followed by mass production at the end of the year or the beginning of 2020, Wei disclosed,” Chen and Shen report. “As high as US$25 billion will be invested in TSMC’s 5nm production ramp-up, said Wei, without giving a specific timeframe.”
Read more in the full article here.
MacDailyNews Take: So, this year’s expected A12 will be 7nm and, likely, next year’s A13, too.
SEE ALSO:
Apple supplier invests $25 billion in future A-series chips – June 21, 2018
<a href="http://macdailynews.com/2018/04/23/tsmc-ramps-up-production-of-apples-next-gen-7nm-a12-soc/"TSMC ramps up production of Apple’s next-gen 7nm A12 SoC – April 23, 2018
[Attribution: AppleInsider. Thanks to MacDailyNews Reader “Fred Mertz” for the heads up.]
WOW NANO-meters. Is going from 7 to 5 really a big power savings? Seems like only yesterday we were excited to go sub 20nm. What is the power impact of a 7nm chip vs 5nm I wonder?
At 5nm rather than 7, you can put 71% more transistors into the same space. That is significant.
Not so sure it’s all that beneficial, for dicing losses, pic machine damage, and so forth will decrease chip yield, which means the cost math at the water level isn’t merely the relative area.
Water … autocorrect error: meant wafer
Nobody caught my big mistake. The number of circuits on a chip goes up in proportion to the square of the etching size. It isn’t linear.
Actually, I did say “area”.
But my point still remains the same – – as much good as it does to shrink the die to save money, since the yields invariably go down, the cost savings isn’t as big as one would hope.
Plus there’s also still “real estate” issues with getting power & data to & from a smaller chip: the leads have a finite size to them, as does also the bonding sites — these are also another limiting factor that often get overlooked on “percent smaller” claims.
Plus there’s also the thermal management factor: chip efficiency can improve with shrinkages, but it doesn’t improve at the SQUARE of the dimension (area factor again): any savings from being smaller may very well be lost when one has to then add a better heat spreader…especially if one has to change to a more expensive solution to get the heat extracted… TIM made from Gold vs Indium, a TPG insert, etc.
Have Apple’s SoCs already reached a point of diminishing returns. It’s likely Wall Street has already decided so. So far, Apple is the ONLY major tech company to have already hit a revenue wall for the rest of the year. What are you doing, Apple? Why no further gains? Why no more great ideas out of Cupertino?
Qualcomm’s pockets must be nearly as deep as Apple’s to make that jump to 5nm.
Apple needs to look for something other than just iPhones in its future.
@laughing_boy Now we know why they call you laughing boy.
Better still why he calls himself laughing boy.
Anyway you measure it, still a smaller node than Intel.